Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modem electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks”. Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. For ease of access and management the erase blocks of a non-volatile memory device are typically arranged in “banks” or segments.
FIG. 1 shows a simplified diagram of a Flash memory 100 of the prior art. The Flash memory 100 has an address interface 104, a control interface 106, and a data interface 108. Internally to the Flash memory device a control state machine 110 directs internal operation of the Flash memory device; managing the Flash memory array 112 and updating RAM control registers and non-volatile erase block management registers 114. The RAM control registers and tables 114 are utilized by the control state machine 110 during operation of the Flash memory 100. The Flash memory array 112 contains a sequence of memory banks or segments 116. Each bank 116 contains a series of erase blocks 118.
During use of a non-volatile erase block memory device, errors or faults commonly will appear in erase blocks. For this situation, additional erase blocks are typically associated with the memory array beyond the number that is necessary for the memory device to contain its specified data size. The additional extra erase blocks are then utilized by the non-volatile memory device for the replacement of erase blocks that become damaged or corrupted, thus ensuring the availability of the specified data storage during the expected lifetime of the non-volatile erase block memory device. These additional erase blocks are also known as redundant erase blocks or replacement erase blocks.
FIG. 2 shows a simplified block diagram of a redundant block control circuitry 200 and redundant erase blocks 202 of a Flash memory of the prior art. In FIG. 2, the redundant block control circuitry 200 is coupled to a number of redundant erase blocks 202 that are associated with each memory bank 204 (in the Flash memory of FIG. 2, 6 redundant erase blocks for each memory bank of 64 erase blocks). The redundant block control circuitry 200 contains a series of block fuse sets and SRAM latches (not shown) that each correspond to and activate a single redundant erase block 202 in a specific memory bank 204. When a general use erase block 206 of one of the main array banks 204 becomes damaged and must be replaced, an external controller or processor (not shown) operates the Flash memory control circuitry (not shown) to program a redundant block fuse set to replace the damaged main array erase block 206 with a redundant erase block 202. Afterwards, if an address is received at the Flash memory address interface (not shown) that addresses a damaged general use erase block 206, the programmed fuse set (not shown) disables the access to the general use erase block 206 in the main memory array bank 204 and activates its corresponding redundant erase block 202 in the memory array bank 204 for access via the redundant erase block select lines 208. The redundant erase blocks 202 are generally specific to a memory array bank 204 and can only be used to replace damaged erase blocks in that memory array bank. Therefore, a memory array bank 204 that accumulates more damaged general use erase blocks 206 than redundant replacement erase blocks 202 can no longer be repaired even though unused redundant erase blocks 202 exist in other memory array banks 204.
Because of this replacement erase block repair mechanism and the specificity of the redundant erase blocks to the memory banks, manufacturers must construct a much larger memory device and internal memory array banks than are necessary in order to guarantee a minimum available device size. Additionally, because they are not part of the main memory array addressing scheme, until the redundant erase blocks of a non-volatile erase block memory device are utilized in a repair they are unavailable for general use by the end user of the memory device even though they are present in the memory array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved non-volatile memory erase block addressing scheme.